1. Field of the Invention
The present invention relates to a method of reading a flash memory cell, a NAND-type flash memory apparatus, and a NOR-type flash memory apparatus and, more specifically to a method of determining a programmed state or an erased state of a flash device.
2. Discussion of Related Art
In general, a method of reading a flash device uses the fact that a threshold voltage in a state where electrons are stored in a floating gate is about 1V and a threshold voltage in a state that holes are stored in the floating gate is −3V.
Now, the corresponding read operation in a conventional method will be described with reference to the drawings.
FIG. 1 is a circuit diagram for explaining a conventional method of reading a flash device.
FIGS. 2A and 2B are conceptual views for explaining a conventional method of reading a flash device.
FIG. 3 is a conceptual view illustrating a change of a voltage in accordance with a conventional method of reading a flash device.
For the sake of convenience, the description will be made based on the reading of a state of a cell A shown in FIG. 1. The cell A is referred to as an “A cell” or a “selected cell.” A bit line and a word line connected to the selected cell are referred to as a “bit line Sel B/L” and a “word line Sel W/L,” respectively. A non-selected bit line and a non-selected bit line are referred to as a “pass bit line Pass B/L” and a “pass word line Pass W/L.”
Firstly, voltages applied to the respective lines to read the state of the A cell of the flash device will be described with reference to FIGS. 1, 2A, 2B, and 3. And then, the method of reading the state information of the flash memory cell.
In order to read the state of the A cell, a voltage of 1V is applied to the selected bit line Sel B/L, and a ground voltage of 0V is applied to the pass bit lines Pass B/L. In addition, a voltage of 0V is applied to the selected word line Sel W/L, and a pass voltage Vpass is applied to the pass word lines Pass W/L. A voltage of 0V is applied to the common source line. In other words, a voltage of 0V is applied to word lines sharing the selected cell, and a pass voltage is applied to word lines sharing the non-selected cells.
When the selected cell is in the erased state, the A cell is turned on to discharge the voltage charged in the selected bit line Sel B/L. In other words, the switch shown in FIG. 2B is turned on to discharge the voltage charged in the line. As shown FIG. 3, the discharged voltage is equal to a product of a cell current Icell flowing the selected cell and a determination time T divided by a line capacitance C (see line E1 in FIG. 3). The corresponding voltage drop is represented as Icell×T/C.
On the other hand, when the selected cell is in the programmed state, the A cell is turned off to maintain the voltage of the selected bit line Sel B/L at the level of the charged voltage. In other words, the switch shown in FIG. 2B is turned off to maintain the voltage of the line at the level of the charged voltage. As shown in the dotted line in FIG. 3, it is necessary that the selected bit line Sel B/L is maintained at the voltage (charged voltage) of 1V (see the dotted line in FIG. 3). However, in the selected bit line Sel B/L, a certain voltage is discharged due to leakage currents of the other devices that are connected to the bit line Sel B/L, (see line P1 in FIG. 3). Namely, when the selected cell is in the programmed state for preventing the current from flowing, as shown in FIG. 3, there is the discharge phenomenon of the voltage corresponding to a product of the leakage current Ileak and a determination time T divided by a line capacitance C. The corresponding voltage drop due to the current leakage of the devices connected to the selected bit line Sel B/L is represented as Ileak×T/C.
As shown in FIG. 3, the discharge phenomenon exists due to the current leakage of the other devices connected to the line even in the programmed state as well as in the erased state of the selected cell. As a result, the so-called information resolution capability of the cell is lowered, and performance of the flash device is lowered due to delay of determination time. Therefore, the competitiveness of products is weakened. In addition, there is another problem that the leakage current is generated in an information determination unit itself as well as non-selected array. In a highly integrated device, suppression of the leakage current has been a matter of great concern.